[Libre-soc-bugs] [Bug 1072] implement fcvt/fmv instructions in ISACaller (ls006)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1072

--- Comment #32 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Jacob Lifshay from comment #31)
> yeah, I can implement hdl too, it shouldn't be all that complex, maybe 2-3
> days work, assuming soc.git already has basic support for fp ops
> (reading/writing FPRs and FPSCR).

actually closer to 1-2 days since iirc fcvtfg basically already exists in
ieee754fpu

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