[Libre-soc-bugs] [Bug 1072] implement fcvt/fmv instructions in ISACaller (ls006)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1072

--- Comment #25 from Jacob Lifshay <programmerjake at gmail.com> ---
I added tests for the FPSCR output generated by the JS tests, previously FPSCR
was completely ignored.

I fixed fcvttg* FPSCR computation and while I was at it, I changed the overflow
output to only be set when the result actually overflows rather than just
rounds -- previously overflow was set whenever the input value wasn't equal to
the output value, now overflow is set only when the rounded
(trunc/floor/ceil/etc.) input value isn't equal to the output value.

https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=fe2d79d41248ccd0f773298f9f0766bae345bc30

I also changed FPSCRState to act more like the FPSCR register in PowerISA -- it
has 2 bits that are hardwired to always be computed from the other bits, so I
changed FPSCRState to also do that, though there is an opt-out flag you can
pass if you have a fpscr value and just want to decode it without changing the
value.

https://git.libre-soc.org/?p=openpower-isa.git;a=shortlog;h=89a6d373d313df05d8a424178974d9593839f622

commit 89a6d373d313df05d8a424178974d9593839f622
Author: Jacob Lifshay <programmerjake at gmail.com>
Date:   Mon May 15 23:53:40 2023 -0700

    fcvttg*: test FPSCR output

commit 0f21df082b191f27c61de61e1746d842e9685dcf
Author: Jacob Lifshay <programmerjake at gmail.com>
Date:   Mon May 15 23:50:52 2023 -0700

    fix fcvttg* overflow/FPSCR computation

commit 11c3ed1b9b3fc40de0ac6910a4453ce73767371c
Author: Jacob Lifshay <programmerjake at gmail.com>
Date:   Mon May 15 23:48:28 2023 -0700

    fix mis-computed exponent in bfp_CONVERT_FROM_BFP64

commit c08b2ebac840f91fc1f000c721a984293ced8f44
Author: Jacob Lifshay <programmerjake at gmail.com>
Date:   Mon May 15 23:47:03 2023 -0700

    make mis-matched FPSCR errors much easier to read

commit d8f44c10009d84222df48f6ce6f6fd092fad0765
Author: Jacob Lifshay <programmerjake at gmail.com>
Date:   Mon May 15 23:44:22 2023 -0700

    fpscr: rename computed bits -> summary bits since that's what the spec uses

commit c88429bb799867eb7b35f1c30e763b20c41d77ab
Author: Jacob Lifshay <programmerjake at gmail.com>
Date:   Mon May 15 21:34:20 2023 -0700

    auto-compute FPSCR exception summary bits

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