[Libre-soc-bugs] [Bug 1083] update to DD FFirst Mode binutils PowerDecoder

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1083

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=f3cfeda33bb90b218f6e7e8995553d4b0ceb044f

RG and VLi move to bit 19 (Mode[0]) for consistency

 |6 | 7 |19:20|21 | 22:23   |  description     |
 |--|---|-----|---|---------|------------------|
-|/ | / |0 RG | 0 | dz  sz  | simple mode                      |
-|/ | / |0 RG | 1 | dz  sz  | scalar reduce mode (mapreduce) |
-|zz|SNZ|1 VLI|inv|  CR-bit | Ffirst 3-bit mode      |
-|/ |SNZ|1 VLI|inv|  dz sz  | Ffirst 5-bit mode (implies CR-bit from result) |
+|/ | / |RG 0 | 0 | dz  sz  | simple mode                      |
+|/ | / |RG 0 | 1 | dz  sz  | scalar reduce mode (mapreduce) |
+|zz|SNZ|VLI 1|inv|  CR-bit | Ffirst 3-bit mode      |
+|/ |SNZ|VLI 1|inv|  dz sz  | Ffirst 5-bit mode (implies CR-bit from result) |

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