[Libre-soc-bugs] [Bug 1039] add hardware-cycle-accurate stastistical modelling to ISACaller for an in-order core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1039

--- Comment #10 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Dmitry Selyutin from comment #9)
> I'll perhaps revisit the trace format to make it more usable for
> lookup/split,

yes it should easily be parseable it 2-3 lines, nothing sophisticated
needed. i know you like (and importantly understand) regexes, do try
to keep it simple :)

format

"r or w"
"target" (regfile name GPR FR CR CRf XER MSR FPSCR SPRf SPRs" or MEM)
"reg or memaddr"
"elwidth or memwidth"
"element offset" (not for rMEM or wMEM)

> but at this stage insndb is not needed. Again, the former
> commits are for future purposes only.

ack appreciated.

CR is the whole CR, that will be one port on its own, assume max 1R1W
CRf is one 4-bit port, assume 3R3W of these
GPR is int regfile assume 4R1W
FPR is FP regfile assume 3R1W
XER is special assume 1R1W
FPSCR is special assume 1R1W
SPRf is FAST spr, assume 3R3W
SPRs is SLOW spr, assume 1R1W

MEM ignore for now.

so here:

 175         while len(possible) < 3 and

becomes:

     while possible_cr < 3

and

     while possible_gpr < 4

etc. i.e. the instruction can only proceed once all regs have been read,
but there is limited ports so it can take several cycles, but each one
read you can take it out the set.

when the set is empty then all operands are read, it can issue.

real simple.

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