[Libre-soc-bugs] [Bug 1039] add hardware-cycle-accurate stastistical modelling to ISACaller for an in-order core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1039

--- Comment #8 from Dmitry Selyutin <ghostmansd at gmail.com> ---
Since I already started changing insndb to make it reusable for any module
which needs either assembly or disassembly, I decided to complete these
changes. Regardless of the current task, the changes seem to be good for other
future needs.

These works seem to be completed now:
https://git.libre-soc.org/?p=openpower-isa.git;a=shortlog;h=refs/heads/insndb-asm-dis.
As we discussed, I won't use these changes in scope of this task, unless
necessary later (certainly not now).

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