[Libre-soc-bugs] [Bug 1072] implement fcvt/fmv instructions in ISACaller (ls006)

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu May 11 09:14:09 BST 2023


--- Comment #21 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Jacob Lifshay from comment #19)
> (In reply to Jacob Lifshay from comment #18)
> > bit 0 is the first fractional bit, since that is
> > what the PowerISA spec expects.
> actually bit 0 is the lsb integer bit, bit 1 is the first fractional
> bit...adding a todo to fix that.

fixed! I also added through tests of SelectableMSB0Fraction

commit 8e56c6b9468925a44aaa805ff05605ec5cc369a5
Author: Jacob Lifshay <programmerjake at gmail.com>
Date:   Thu May 11 01:05:04 2023 -0700

    SelectableMSB0Fraction is now basically complete and correct afaict

next is adding smoke tests of the rest of fp_working_format, and deciding if we
want the bfp_* functions to be manually translated from mostly english prose to
pseudocode (preferred) or to python...this is *not* intended for submission to
the ISA WG as a change of the spec, but just that being in pseudocode makes it
easier for us to implement them. I'll add comments to that effect in the

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