[Libre-soc-bugs] [Bug 1039] add hardware-cycle-accurate stastistical modelling to ISACaller for an in-order core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1039

--- Comment #6 from Dmitry Selyutin <ghostmansd at gmail.com> ---
insndb needs to be extended with support for keeping some information after the
assembly process took place. Right now we construct instruction on-the-fly;
once the instruction is assembled, we simply have 32 or 64 bits (depending on
prefix).

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