[Libre-soc-bugs] [Bug 1073] Microwatt verilator sim - setting up chroot and documentation

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon May 1 14:48:32 BST 2023


--- Comment #11 from Andrey Miroshnikov <andrey at technepisteme.xyz> ---
(In reply to Luke Kenneth Casson Leighton from comment #10)
> an exception.  look up the table somewhere...  page 1067 rings 
> bell somewhy.

Found the table you mentioned:
PowerISA v3.1B pdf:
Section 7.5 Interrupt Definitions

PDF page 1302 (spec page 1276)
Figure 70. Effective address of interrupt vector by
interrupt type:
00..0000_0800 | Floating-Point Unavailable

So I'm guessing this is something about floating-point hardware not being

Looking at the bram.dump line in detail:
pc ff000000 insn ffffffff msr 8000000000000001

Does it mean:
PC: ff00_0000
decoded instruction: ffff_ffff (I'm guessing this is incorrect decoding,
because the word is not an instruction but data, or empty)
MSR value: 8000000000000001
Machine State Register (Book III, Section 4.2.1):
bit0: 0 (32-bit mode) / 1 (64-bit mode)
... (ignoring the rest)
bit63: 0 (big-endian) / 1 (little-endian)

So just out of reset the processor is:
- in 64-bit thread mode, little-endian
- PC at ff00_0000
- Current instruction is ffff_ffff (not a valid instruction?)

It looks like (as you have pointed out already), the processor is expecting
instructions at ff00_0000 (reset address), but the program binary is not there.
It goes through addresses ff00_0000, ff00_0004, ff00_0008, but continues to
find no instructions.

What do these statements mean:
rd @ 00000100 di         48000000 sel ff ...H....

Read value at address 0000_0100 is 4800_0000?

Sorry for being dumb, I think I understand the problem, but I don't know how to
go about pointing the cpu to the right place.

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