[Libre-soc-bugs] [Bug 1116] evaluate, spec, and implement Vector-Immediates in SVP64 Normal

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1116

--- Comment #6 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
i have some ideas on this to reduce decode complexity.

1. overload sv.b yes really sv.b so that it sets a bit in
   SVSTATE "if the next instruction is prefixed then get
   the immediate-constants from CIA-MAXVL//2"
2. if that bit is set (which should be transient) then
   next instruction clears it.

a small unconditional relative-branch would leave a hole
in the instruction stream, and the nice thing is, it's an
*actual* branch not an implicit one.

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