[Libre-soc-bugs] [Bug 1116] evaluate, spec, and implement Vector-Immediates in SVP64 Normal

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1116

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #3)
> (In reply to Jacob Lifshay from comment #2)
> > it can be treated like a jump so the next instruction address gets added to
> > the branch target buffer and the next-pc logic will speculatively fetch from
> > the correct location on the next cycle, even before decoding has started.
> 
> actually, that doesn't work since it needs to fetch all the immediate bytes
> too, not just skip over them.

hence why i'm scared of introducing extra dependencies, increasing
gate-latency, in parallel-decode (such as elwidth, *especially* BF8/FP16
differences).

and why i said that this should only be in "advanced" implementations,
and/or at lower-clock-rate machines such as 3D GPUs, where ~1.5 ghz max
clock rate will not be a problem.

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