[Libre-soc-bugs] [Bug 1116] New: evaluate, spec, and implement Vector-Immediates in SVP64 Normal

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1116

            Bug ID: 1116
           Summary: evaluate, spec, and implement Vector-Immediates in
                    SVP64 Normal
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-soc-bugs at lists.libre-soc.org
   NLnet milestone: NLnet.2022-08-107.ongoing
 total budget (EUR) 2000
  for completion of
       task and all
          subtasks:
   budget (EUR) for 2000
         this task,
          excluding
  subtasks' budget:
    parent task for 1027
 budget allocation:

https://bugs.libre-soc.org/show_bug.cgi?id=1092#c18

the idea is that any sequence of immediates may be repeated
*as a vector* in the instruction stream.  some serious caveats
are needed as this is right at the Decode Phase.

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