[Libre-soc-bugs] [Bug 1039] add hardware-cycle-accurate stastistical modelling to ISACaller for an in-order core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1039

--- Comment #21 from Andrey Miroshnikov <andrey at technepisteme.xyz> ---
(In reply to Dmitry Selyutin from comment #19)
> I guess readeregs and writeregs are just like this:
> 
> def regfilter(regs, type):
>     return filter(lambda reg: reg.type == type, regs)
> 
> regs = tuple(...)
> readregs = tuple(regfilter(regs, "r"))
> writeregs = tuple(regfilter(regs, "w"))

Thanks, my code was a bit more naive (if hazard.action = 'r' return hazard
etc.). Will update when I have time.

(In reply to Dmitry Selyutin from comment #20)
> Andrey, I've reassigned this task to you, since you're working on it, any
> objections?

Sure. When I get the model to work, I may need more guidance however.

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