[Libre-soc-bugs] [Bug 1039] add hardware-cycle-accurate stastistical modelling to ISACaller for an in-order core

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Fri Jun 2 13:57:28 BST 2023


--- Comment #19 from Dmitry Selyutin <ghostmansd at gmail.com> ---
I guess readeregs and writeregs are just like this:

def regfilter(regs, type):
    return filter(lambda reg: reg.type == type, regs)

regs = tuple(...)
readregs = tuple(regfilter(regs, "r"))
writeregs = tuple(regfilter(regs, "w"))

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