[Libre-soc-bugs] [Bug 1039] add hardware-cycle-accurate stastistical modelling to ISACaller for an in-order core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1039

--- Comment #19 from Dmitry Selyutin <ghostmansd at gmail.com> ---
I guess readeregs and writeregs are just like this:

def regfilter(regs, type):
    return filter(lambda reg: reg.type == type, regs)

regs = tuple(...)
readregs = tuple(regfilter(regs, "r"))
writeregs = tuple(regfilter(regs, "w"))

-- 
You are receiving this mail because:
You are on the CC list for the bug.