[Libre-soc-bugs] [Bug 1039] add hardware-cycle-accurate stastistical modelling to ISACaller for an in-order core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1039

--- Comment #30 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Andrey Miroshnikov from comment #22)
intentionally only pushed the necessary changes to get the code to run.

> What is the issue stage really meant to be?

in a single-issue Scalar core? a dummy placeholder MODELLING the
fact that the HDL issued a single instruction.

i did tell you that all of this is far simpler than everyone tasked
with it has made it out to be.

well done getting to the absolutely critical "iterative feedback"
phase. didn't take much, did it?

-- 
You are receiving this mail because:
You are on the CC list for the bug.