[Libre-soc-bugs] [Bug 942] next things to work on -- bigint rsa mul algorithm for bigint presentation

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Tue Oct 4 19:52:58 BST 2022


--- Comment #2 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #1)
> (In reply to Jacob Lifshay from comment #0)
> > It would be run on a simplistic model cpu with 1 256-bit simd add unit and 1
> > 256-bit wide-mul unit (the model would be adjustable) and scalar units, I
> > would create a simulator for that, the simulator would cover ALU pipeline
> > timing and dependencies but not much else.
> everything but this is a great idea.  there's no point spending time
> on doing hardware-cycle-accurate pipelining when cavatools is specifically
> designed to do exactly that, and already has the infrastructure in place.
> any time spent on developing any hardware-cycle-accurate simulations is
> therefore both time and money completely wasted.

the point is to have pretty animations of how data moves in the cpu so people
understand how the wide-mul merging works (which requires something to
construct those animations), not to have specific timing for exact performance

the sw to construct those animations is the simplistic SIMD ALU simulator --
imho spending a week writing that is waay better than creating animations by
hand that only cover 1 specific run of 1 specific algorithm and is likely to
have mistakes because it was done by hand.

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