[Libre-soc-bugs] [Bug 942] next things to work on -- bigint rsa mul algorithm for bigint presentation

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=942

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #0)

> It would be run on a simplistic model cpu with 1 256-bit simd add unit and 1
> 256-bit wide-mul unit (the model would be adjustable) and scalar units, I
> would create a simulator for that, the simulator would cover ALU pipeline
> timing and dependencies but not much else.

everything but this is a great idea.  there's no point spending time
on doing hardware-cycle-accurate pipelining when cavatools is specifically
designed to do exactly that, and already has the infrastructure in place.
any time spent on developing any hardware-cycle-accurate simulations is
therefore both time and money completely wasted.

also as i have repeated many times timing is *not* part of the bitmanip
NLnet proposal because the financial cost to NLnet would be an order of
magnitude larger and put the entire project at risk to even attempt to
tackle timing.

     *this is not up for discussion*.

please do not *under any circumstances* spend *any* time attempting to
show timing or any level of performance other than reduction in instruction
count and reduction in complexity at this very early stage.

the entire focus at the moment is on power reduction and complexity reduction.
*NOT* in ANY WAY on TIMING.  at all.

the algorithm implementations, great idea.

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