[Libre-soc-bugs] [Bug 784] Implement cl* instructions for carry-less operations
bugzilla-daemon at libre-soc.org
bugzilla-daemon at libre-soc.org
Fri May 6 04:24:42 BST 2022
https://bugs.libre-soc.org/show_bug.cgi?id=784
--- Comment #41 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Jacob Lifshay from comment #40)
>
> ah, missed that.
>
> apparently yosys isn't optimizing the adder chain to just 1 add per clock
> cycle
fixed that:
commit 4ee201e6cae8475621647f7b3b9839292ed0b46f (HEAD -> master, origin/master)
Author: Jacob Lifshay <programmerjake at gmail.com>
Date: Thu May 5 20:10:32 2022 -0700
split step counter into clock and substep
this allows substep to be completely optimized away by yosys for
CLDivRemFSMStage
I ran the comparison by running:
python src/nmigen_gf/hdl/test/test_cldivrem.py -k test_64_step_8
yosys <<'EOF'
read_rtlil sim_test_out/__main__.TestCLDivRemFSM.test_64_step_8/0.il
flatten
synth
;;;
stat
ltp -noff
EOF
old unsplit step algorithm:
https://git.libre-soc.org/?p=nmigen-gf.git;a=commit;h=e59b7ccf6c066fc0ecac6410e9b6447d5af77533
Number of cells: 5046
$_ANDNOT_ 302
$_AND_ 67
$_MUX_ 3283
$_NAND_ 12
$_NOR_ 77
$_NOT_ 323
$_ORNOT_ 61
$_OR_ 58
$_SDFFE_PP0P_ 72
$_SDFF_PP0_ 197
$_SDFF_PP1_ 1
$_XNOR_ 149
$_XOR_ 444
Longest topological path in top (length=36):
New algorithm where step is split into clock and substep:
https://git.libre-soc.org/?p=nmigen-gf.git;a=commit;h=4ee201e6cae8475621647f7b3b9839292ed0b46f
Number of cells: 4818
$_ANDNOT_ 290
$_AND_ 45
$_MUX_ 3297
$_NAND_ 6
$_NOR_ 68
$_NOT_ 196
$_ORNOT_ 41
$_OR_ 62
$_SDFFE_PP0N_ 6
$_SDFFE_PP0P_ 70
$_SDFF_PP0_ 190
$_SDFF_PP1_ 1
$_XNOR_ 136
$_XOR_ 410
Longest topological path in top (length=31):
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