[Libre-soc-bugs] [Bug 784] Implement cl* instructions for carry-less operations

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=784

--- Comment #40 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #39)
> (In reply to Jacob Lifshay from comment #38)
> 
> >    Number of cells:               5046
> 
> woo, halved.
> 
> > I don't know of a fast and easy way to get yosys to output latency numbers,
> > so I'm not testing that.
> 
> there's a command ltp (longest path?)
> http://yosyshq.net/yosys/cmd_ltp.html

ah, missed that.

apparently yosys isn't optimizing the adder chain to just 1 add per clock cycle
(maybe because it's in a feedback loop so it's not easy to deduce that the low
bits of the step counter will always be zeros). I have an idea of how to fix
that...split the step counter into two parts: 1 that counts number of clock
cycles ahd 1 that counts steps within a clock cycle (not necessarily a power of
2). the within-a-clock-cycle step counter will not be stored in the saved_state
register since it's known to always be zero (formal proof will assert that).
the clock cycle counter should be trivially optimizable by yosys to 1 adder.

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