[Libre-soc-bugs] [Bug 828] New: 2RW and 1RW SRAM compiler development

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=828

            Bug ID: 828
           Summary: 2RW and 1RW SRAM compiler development
           Product: Libre-SOC's second ASIC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: source code
          Assignee: lkcl at lkcl.net
          Reporter: staf at fibraservi.eu
                CC: libre-soc-bugs at lists.libre-soc.org
   NLnet milestone: ---

After designing the SRAM cell in bug #827 the compiler need to be made. This
task will consist of the following subtasks:

* layout helper functions in PDKMaster to ease layout
* Update layout of 1RW subblocks for optimized 1RW SRAM cell and 
* Update layout of subblocks to handle double bitline pair for 2RW dual part
compiler.

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