[Libre-soc-bugs] [Bug 827] 2RW SRAM cell design; 1RW SRAM cell improvement

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=827

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |lkcl at lkcl.net
    NLnet milestone|---                         |NGI.POINTER.Gigabit.ASIC
             Blocks|                            |690


Referenced Bugs:

https://bugs.libre-soc.org/show_bug.cgi?id=690
[Bug 690] NGI POINTER Gigabit Router ASIC, top level milestone
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