[Libre-soc-bugs] [Bug 781] create wrapper register files around 1R-or-1W SRAMs

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=781

--- Comment #5 from Cesar Strauss <cestrauss at gmail.com> ---
Without going for multiple clocks, I think it is maybe possible to implement a
1W1R memory block, using a single clock, using four 1RW memory blocks of the
same size.

It would go like this:

The first 1RW memory block would alternate between read and write. For
instance, write on even cycles, read on odd cycles. Let's call it an 1eW1oR
memory.

The second memory, on odd cycles, copies the value just written on the first
memory, and allows reading on even cycles (1oW1eR). The "odd-only" write port
is tied, but the read port (on even cycles) is free.

That way, we can still write only on even cycles, but can now read both on even
and odd cycles: 1eW1R

Now, repeat this, to make an 1oW1R. Together with a "Live Value Table", we
would get a full 1W1R memory out of four 1RW memories (plus multiplexers, and
FFRAM for the LVT).

I suspect the area cost of this 1W1R would not compare with one based on a
single 2RW memory block, but, in the absence of this, can compete, at least in
terms of risk, with a DDR 1RW memory implementation.

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