[Libre-soc-bugs] [Bug 781] create wrapper register files around 1R-or-1W SRAMs

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=781

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #3)

> i forgot we're not using skywater130, oops...thanks lkcl for pointing that
> out in the meeting today!

if we did 32 bit Power we stand a slim chance rather than no chance of
fitting into 10 mm^2 of sky130 MPWs.

(In reply to Cesar Strauss from comment #2)
> By any chance, is the SRAM in question exactly the same as the one on the
> chip, which is described on bug 502?

no it was part of a 4k suite of SRAM cells, and 1R-or-1W

> If so, I can adopt the simulation model on bug 502, comment 8.

assuming that Staf provides the cell, yes.

that one is a 1R *OR* 1W in theory with the back to back cell idea
you came up with, yes.  the trick with that will be to ensure all
possible permutations of reads and writes over 3 clock cycles
will work as 1R *AND* 1W.

clock 1      clock 2      clock 3
no r no w    no r no w    no r no w
r 
      w
r     w
             r
r            r
      w      r
r     w      r
                   w
r                  r

etc. basically 64 permutations of 2 actions (r and w) over 3 cycles.
msybe 256 over 4 cycles.

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