[Libre-soc-bugs] [Bug 724] Determine required memory compiler developments

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=724

--- Comment #23 from Staf Verhaegen <staf at fibraservi.eu> ---
(In reply to Luke Kenneth Casson Leighton from comment #20)
> (In reply to Staf Verhaegen from comment #19)
> > You can't just write a
> > digital wrapper around a SRAM cell to get a SRAM block which seems a wrong
> > assumption made in #781.
> 
> i believe Cesar was intending to do alternating-clocks at the top level
> (the Memory Block) on a *pair* of Memory Blocks.

You can indeed have the SRAM run at double the clock frequency than the main
chip and that way transform a 1RW block into a 2RW block in the slower clock
domain.

When you do this you need to take care the that P&R handles the timing of these
two clocks properly.
Also if you always want to do a read on the rising edge of the slower clock and
a write on the falling edge it seems not so trivial to be sure about that. You
will need to use the slower clock to decide if the higher clocked SRAM needs to
do a read or write. This is ripe for post P&R timing problems.

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