[Libre-soc-bugs] [Bug 784] Implement cl* instructions for carry-less operations

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=784

--- Comment #1 from Jacob Lifshay <programmerjake at gmail.com> ---
I added CLMulAdd, a combinatorial carry-less multiply-add unit that uses
tree-reduction to do all the XORs in the multiply add, that way, a 64x64 clmul
should have a gate delay of 7 (1 layer of and gates and 6-deep trees of xor
gates).

https://git.libre-soc.org/?p=nmutil.git;a=commitdiff;h=e681da8ca9d8c9ff461eba9f3ff045e40f249dc2

Here's a nice 4x4 clmul that I generated:
https://ftp.libre-soc.org/clmul_4x4.svg

Commands:
python src/nmutil/test/test_clmul.py TestCLMulAdd.test_4x4
yosys <<'EOF'
read_rtlil sim_test_out/__main__.TestCLMulAdd.test_4x4/0.il
flatten
synth
;;;
show -stretch -colors 5 -format svg -prefix clmul_4x4
EOF

-- 
You are receiving this mail because:
You are on the CC list for the bug.