[Libre-soc-bugs] [Bug 724] Determine required memory compiler developments

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=724

--- Comment #14 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Staf Verhaegen from comment #13)
> Just to notify I have seen bug #781 but currently don't have time to give
> technical feedback. I first need to finish Sky130 tape-out of single port
> SRAM which will be very close to be able to make it.

understood.

> Just want to comment now that making a block that does a read followed by a
> write in one clock cycle is more risky than having a dual port RAM where you
> can do the read on one port and a write on the other port in the same clock
> cycle.

redesigning the Libre-SOC Core's access to register files, to take that into
account, forcing all reads *and* writes through a single-access arbitration,
is not a practical option either in terms of the code itself nor in terms of
performance.

the absolute bare minimum that the Libre-SOC Core's code has been designed
to is that the read port(s) are completely independent of the write port(s)
and that the absolute bare minimum of each is one (1).

redesigning the Arbitration (regfile access protection logic)
is neither practical nor desirable.


> It will take up more space though.

there are 10 pipelines, some require 3x INT regfile reads, and a minimum
1x INT regfile writes, where LD/ST requires 2x INT regfile writes.

any space saved by is already overwhelmed by the size of the broadcast
bus logic.

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