[Libre-soc-bugs] [Bug 764] Documentation of I/O Core/Pad JTAG Tests

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=764

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Andrey Miroshnikov from comment #4)
> Updated the documentation related to the pinmux block (Section 4):
> https://libre-soc.org/docs/pinmux/

looks great, the only thing the numbering in each cell is wrong, here
https://libre-soc.org/docs/pinmux/xgpio-mem-layout.jpg.pagespeed.ic.p5E850LcdR.webp

it should be

add/row
0          7  6  5  4  3  2  1  0
1         15 14 13 12 11 10  9  8

and here:

For example, if 16 GPIOs are instantiated and 64-bit data bus is used, GPIOs
0-7 are accessed via address 0, whereas GPIOs 8-15 are accessed by address 0.

should be:

For example, if 16 GPIOs are instantiated and 64-bit data bus is used, GPIOs
0-7 are accessed via address 0, whereas GPIOs 8-15 are accessed by address 1.

-- 
You are receiving this mail because:
You are on the CC list for the bug.