[Libre-soc-bugs] [Bug 698] ls180 ASIC test tasks

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=698

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
amplifier:

ahh component sourcing, deep joy. can you put the part characteristics on the
bugtracker
i will have a look.  current voltage frequency etc.


the CPU is programmable only by JTAG which is Microwatt DMI Interface.

    https://git.libre-soc.org/?p=soc.git;a=tree;f=src/soc/debug;hb=HEAD

full JTAG Boundary Scan also added.

   
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/jtag.py;h=4b4f17a97d672c3f22b668008a1c058ac2500da6;hb=HEAD#l75

yes really, that simple (not so much in litex which was 3 months hell)

> My colleagues from LIP6 are willing to test basic functionalities of the chip through JTAG interface. I guess for that they need a digital analyser, a digital wayform generator and/or a FPGA board.

openocd id check should work fine.

   
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/test/openocd.cfg;hb=HEAD

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