[Libre-soc-bugs] [Bug 236] Atomics Standard writeup needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=236

--- Comment #43 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
excellllent, ok.

so IBM decided to use "cache barriers" which needs to be determined if
that is directly equivalent to lr/sc's aq/rl flags.

we also need to know if multiple atomic operations can
be multi-issue in-flight (i seem to recall POWER9 is 8-way multi-issue?)

also we need to know what the granularity of internal single-locking
is, by that i mean that if there are multiple requests to the same
{insert thing} then it is 100% guaranteed that, like intel, only
one will ever be serviced.

i suspect, from reading the Power ISA Spec, that {thing} is a Cache
Block.

however that needs to be explicitly determined by deliberately hammering
a POWER9 core with requests at different addresses, varying the differences
and seeing ifthe throughput drops to single-contention.

at exactly the same address is no good, we can assume that will definitely
cause contention.

the other important fact to know is, how does the forward-progress guarantee
work, i.e. how do these "cache barriers" work and i suspect they are similar
to IBM's "Transactions". there is probably an internal counter/tag which goes
up by one on each lwsync.

other architectures are not exacctly of no interest but please really there is
only 2-3 days left before this bugreport gets closed so focus on POWER9

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