[Libre-soc-bugs] [Bug 826] Trial run of ethmac (freecores) layout.

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=826

--- Comment #14 from Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr> ---
(In reply to Luke Kenneth Casson Leighton from comment #13)
> (In reply to Jean-Paul Chaput from comment #10)
> > After a first basic run with the Yosys generated SRAM, it appears that the
> > SRAM takes up 42% of the area for the DFF only. If all the paraphernalia of
> > address decoding and output muxing is added we should be close to 60%.
> 
> as there is not an actual ASIC being manufactured this is not such a big
> concern.

  Yes and no... We won't do the ASIC but still plan to submit a
  mini-design to the Google/SkyWater MPW program. I preemptively
  reply to your question : yes the SkyWater I/O pads are too slow
  to run the ethmac at nominal speed. But we will try to run it slower
  just to check the whole design.
    On a more general side, I think that some people may not have
  access to SRAM optimized block and still rely on Yosys generated
  ones, so having a dedicated placer should be beneficial for the
  community at large.

> > So, would it be possible to have a SRAM of 256 words of 32 bits,
> > conforming to the following interface:

  I leave that up to Staf if he wants to still do it.

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