[Libre-soc-bugs] [Bug 236] Atomics Standard writeup needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=236

--- Comment #20 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #19)
> (In reply to Luke Kenneth Casson Leighton from comment #17)
> > conclusion: oops.  it's ok for amo* but not ok for amo_rw, that would
> > require a drastic (multi-million-dollar impact) redesign of OpenCAPI.
> 
> well, all that needs to happen is 8/16-bit atomics have to transfer a cache
> block to the cache (if not already there) instead of using opencapi
> atomics...

you're missing the point.

there is no "all that needs to happen" here.  i had not realised
how tightly coupled lwat/stwat are into opencapi (i was half expecting
it)

IBM will not think in terms of "instead of using opencapi".

they have not designed "just a processor" they have designed
"a massive data processing business" where Power ISA is one
tiny component of a much bigger ecosystem.

their immediate thought will not be, "these are great for c++ guarantees"

their immediate thought will be, "how much is this going to **** up our
customers spending billions of dollars on coherent parallel distributed
systems for which OpenCAPI is the bedrock".

bottom line if what is proposed does not have a way to fit into opencapi
it is highly likely to be rejected.

aq and rl (acquire and release) will need to be additional opcodes in
opencapi.

-- 
You are receiving this mail because:
You are on the CC list for the bug.