[Libre-soc-bugs] [Bug 855] add libre-soc to kestrel

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=855

--- Comment #24 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ah.  this was me screwing up in february, replacing a 128-bit spec
for the pipeline output with only XLEN(=64) not XLEN*2.
how in hell's teeth i managed not to spot this when we have so
many unit tests.

mul and div tests all pass.  git pushed.



https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=8aaa3876cc22950271d8e4cf622d1658efe93aef

diff --git a/src/soc/fu/mul/pipe_data.py b/src/soc/fu/mul/pipe_data.py
index
072c5da647451ab77d9938c88664e2becc29e243..ded4c5089a56dd22319a2343324830a9a99bd8f6
100644 (file)
--- a/src/soc/fu/mul/pipe_data.py
+++ b/src/soc/fu/mul/pipe_data.py
@@ -15,8 +15,6 @@ class MulIntermediateData(DivInputData):


 class MulOutputData(FUBaseData):
-    regspec = [('INT', 'o', '0:128'),
-               ('XER', 'xer_so', '32')] # XER bit 32: SO
     def __init__(self, pspec):
         super().__init__(pspec, False) # still input style

@@ -25,6 +23,11 @@ class MulOutputData(FUBaseData):
         self.data.append(self.neg_res)
         self.data.append(self.neg_res32)

+    @property
+    def regspec(self):
+        return [('INT', 'o', "0:%d" % (self.pspec.XLEN)),
+               ('XER', 'xer_so', '32')] # XER bit 32: SO
+

-- 
You are receiving this mail because:
You are on the CC list for the bug.