[Libre-soc-bugs] [Bug 855] add libre-soc to kestrel

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=855

--- Comment #18 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to tpearson from comment #16)
> Very quick update in advance of a more detailed update tomorrow...

no problem

> Tracked the main Zephyr problem down to a specific section of mis-executed
> assembler:
> 
> subf    r9,r29,r31
> addi    r9,r9,999
> lis     r30,8388
> ori     r30,r30,39845
> rldicr  r30,r30,32,31
> oris    r30,r30,58195
> ori     r30,r30,63439
> mulhd   r30,r9,r30
> sradi   r10,r30,7
> sradi   r30,r9,63
> subf    r30,r30,r10
> clrldi  r30,r30,32

if you can get the incoming register values (r9, r29, r30, r31)
i can throw that easily into a unit test for the python-based
Simulator.  bear in mind it doesn't understand pseudo-ops, i
know what lis is but not clridi

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