[Libre-soc-bugs] [Bug 195] Formal correctness framework is needed for Power ISA

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=195

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

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--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
The Power ISA pipelines are done: ALU, Logical, CR, Branch, Shift, SPR,
Mul, Trap - this can be considered completed.

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