[Libre-soc-bugs] [Bug 855] add libre-soc to kestrel

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=855

--- Comment #7 from tpearson at raptorengineering.com ---
OK, so it's not the clock frequency, in simulation the interrupts are never
getting enabled even though the interrupt controller is set up correctly.

Digging further, it looks like when the EE bit of the MSR is set, this never
gets propagated to the actual register store.  This is the bit of assembler
that's supposed to turn the interrupts on:

a6 00 20 7d     mfmsr   r9
00 80 29 61     ori     r9,r9,32768
64 01 20 7d     mtmsrd  r9

In practice, this sets r9 to 0x8000 and tries to run mtmsrd.  The instruction
starts to execute and does in fact set the core.state.MSR4 data field
correctly, but for some reason the write enable for MSR1 is then fired instead
of the write enable for MSR4.  Needless to say, the operational MSR is
unchanged at 0x0 and the pending external interrupts are ignored.

Thoughts?

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