[Libre-soc-bugs] [Bug 855] add libre-soc to kestrel

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=855

--- Comment #4 from tpearson at raptorengineering.com ---
Getting close.  Still chasing down some bugs in interrupt handling...

====================================================
    __ __          __            __
   / //_/__  _____/ /_________  / /
  / ,< / _ \/ ___/ __/ ___/ _ \/ /
 / /| /  __(__  ) /_/ /  /  __/ /
/_/_|_\___/____/\__/_/ __\___/_/ _________
  / ___/____  / __/ /_/ __ )/  |/  / ____/
  \__ \/ __ \/ /_/ __/ __  / /|_/ / /
 ___/ / /_/ / __/ /_/ /_/ / /  / / /___
/____/\____/_/  \__/_____/_/  /_/\____/

====================================================

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 (c) Copyright 2007-2015 M-Labs

 BIOS built on Jul  2 2022 02:38:29
 BIOS CRC passed (23f2a5dc)

 Migen git sha1: 5d8ad08
 LiteX git sha1: 7495d92c

--=============== SoC ==================--
CPU:            LibreSoC @ 60MHz
BUS:            WISHBONE 32-bit @ 4GiB
CSR:            8-bit data
ROM:            52KiB
SRAM:           8KiB
L2:             8KiB
SDRAM:          1048576KiB 32-bit @ 240MT/s (CL-6 CWL-5)

--========== Initialization ============--
Ethernet init...
Initializing SDRAM @0x40000000...
Switching SDRAM to software control

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