[Libre-soc-bugs] [Bug 762] Peripheral Pin Muxing Development

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=762

--- Comment #7 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Andrey Miroshnikov from comment #6)

> This wouldn't quite work as the gpio layout has an additional "i" signal, so
> I'll probably have to keep this one separate. Will need some more thinking
> on that.

yyeah, although the format of the data as far as its memory-mapping
is concerned the csrbus layout looks perfect.

however you will need *another* layout which is the actual
wires-as-connected-directly-to-the-IOPad-Cell.  that one would
not have bank_sel, but would be more like:

         padlayout = (("oe", 1),
                      ("i", 1),
                      ("o", 1),
                      ("puen", 1),
                      ("pden", 1),
                    )

which aside from the pullup/down resistors should be looking remarkably
familiar.

will we want the exact same types as in jtag.tap.IOTypes? i don't
know.  maybe.  will we want puen/pden to be optional? probably,
but not right away, i suggest just keeping it straightforward and
simple, add options later

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