[Libre-soc-bugs] [Bug 763] Work on I/O Core Pad JTAG Tests

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=763

--- Comment #10 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Andrey Miroshnikov from comment #9)
> (In reply to Luke Kenneth Casson Leighton from comment #6)
> > this is taking TDI into the top bit (MSB) and dropping the
> > first bit (LSB). in software:
> 
> This is what I tried to describe (I probably didn't make too much sense did
> I?).

3am for me not much makes sense

> I understood the behaviour, however my question is why are the IDBypassBlock
> and IRBlock shifting new data from the top of their internal shift
> registers, while the IOBlock shifts new data from the bottom?

Officially Not Our Problem (tm).  one to file in the "that's interesting, i'll
make a mental note in case it's relevant some point down the line" bucket.

> (In reply to Luke Kenneth Casson Leighton from comment #7)
>
> The proposed change to test_jtag_tap.py:
> 1. Add the function:
> def reverse_bit_order(word, wordlen):
>     rev_word = 0
>     for bit in range(wordlen):
>         rev_word += ((word >> bit) & 0x1) << (wordlen - 1 - i)
>     return rev_word
> 
> 2. Modify input arg and add if statement:
> def tms_data_getset(dut, tms, d_len, d_in=0, reverse=False):
>     if reverse:
>         # Reverse the data word to transmit MSB-first
>         d_in = reverse_bit_order(d_in, d_len)
> 
> 3. Add "reverse" argument to jtag_read_write_reg()

looks great.

you have commit rights to soc (have all along), you could check
with "ssh gitolite3 at git.libre-soc.org"

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