[Libre-soc-bugs] [Bug 950] pysvp64asm: support insndb-based assembly for SVP64 instructions

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=950

--- Comment #13 from Dmitry Selyutin <ghostmansd at gmail.com> ---
I cannot confirm it yet, but I have a wild guess that some tests might fail due
to the fact that instructions are now fully decoded. Can it be the case? I
compiled some code and it's the same in both master and insndb branch if
compiled; the only thing different is the textual representation. Let's
consider this code:

setvl 0, 0, 5, 1, 1, 1
sv.cmp 0, 1, *4, 14
sv.isel 14,*4,14,1
svstep. 12, 6, 0
sv.isel 10,12,10,1
svstep. 0, 1, 0
bc 6, 3, -0x24

With master branch, it gets converted to this:

.long 0x580009F6 # setvl 0, 0, 5, 1, 1, 1 # setvl 0, 0, 5, 1, 1, 1
.long 0x05400400; cmp 0, 1, 1, 14 # sv.cmp 0, 1, *4, 14
.long 0x05400800; isel 14, 1, 14, 1 # sv.isel 14,*4,14,1
.long 0x59800A27 # svstep. 12, 6, 0 # svstep. 12, 6, 0
.long 0x05400000; isel 10, 12, 10, 1 # sv.isel 10,12,10,1
.long 0x58000027 # svstep. 0, 1, 0 # svstep. 0, 1, 0
bc 6, 3, -0x24


With insndb branch, it gets converted to this:

.long 0x580009F6 # setvl 0,0,5,1,1,1 # setvl 0, 0, 5, 1, 1, 1
.long 0x05400400; .long 0x7C217000; # cmp 0,1,*4,14 # sv.cmp 0, 1, *4, 14
.long 0x05400800; .long 0x7DC1705E; # isel 14,*4,14,1 # sv.isel 14,*4,14,1
.long 0x59800A27 # svstep. 12,6,0 # svstep. 12, 6, 0
.long 0x05400000; .long 0x7D4C505E; # isel 10,12,10,1 # sv.isel 10,12,10,1
.long 0x58000027 # svstep. 0,1,0 # svstep. 0, 1, 0
.long 0x40C3FF70 # bc 6,3,-0x24 # bc 6, 3, -0x24

This should behave in an identical way; however, I still observe failures with
src/openpower/decoder/isa/test_caller_setvl.py. Can my guess be correct? The
reproducer is $(INSNDB=true SILENCELOG=true python3
src/openpower/decoder/isa/test_caller_setvl.py).

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