[Libre-soc-bugs] [Bug 838] sync or at least statically check fields.text, power_decoder, trans/svp64, CSVs between each other

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=838

--- Comment #39 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Dmitry Selyutin from comment #38)
> Forms missing from enumeration: VA2, SVC, SVR.
> Forms not known at all (both 3.0B and 3.1): DQE, TX.
> 
> TX looks like an X-form with TX bit present (cf. mtvsrwz).

yes TX is the extra bit that turns PackedSIMD (VSX) reg
numbers from 5-bit (32 regs) to 6-bit (64 regs).  they
probably put the one extra bit elsewhere, leaving the
5 bits RA RB etc. etc. where they are to avoid the MUXes
just for PackedSIMD [a common hardware decode tactic]

> I've updated the enumeration list:
> https://git.libre-soc.org/?p=openpower-isa.git;a=commit;
> h=08088da82e27a632f7c4c606f1ed2ea3c64658ca

+    VA2 = 38
+    SVC = 39
+    SVR = 40

ehn? how did i miss those, well-spotted :)

> As for unknown forms, which are present only in operands description, -- I
> deliberately skip these for now in the code.

you can guess what happened, can't you - earlier versions of
Power ISA spec had those (v2.06, v2.07) and someone did a cleanup
of the v3.1 spec but forgot to go back and clean up v3.0

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