[Libre-soc-bugs] [Bug 781] create wrapper register files around 1R-or-1W SRAMs

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=781

--- Comment #11 from Cesar Strauss <cestrauss at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #10)
> ah, a single-bit for the "last value", that could be a DFF,
> it is not so costly.

Well, if you want byte-level granularity for writes, you need one DFF per
stored byte, or 8 DFF per stored 64-bit register...

The XOR trick doesn't need any DFF RAM, but costs 6 x 1RW blocks. It works like
this:

1) Like before, there are two memories, each reading on every cycle, and
writing on alternate cycles (2 x 1RW each)
2) Instead of a MUX, the read port is a direct XOR of the two memories.
3) Writes happens in two cycles:
First, read the current value of the *other* memory, at the write location.
Then, on *this* memory, write that read value, XORed with the desired value.

This recovers the desired value when read:
  (other XOR desired) XOR other = desired

We do need an extra read port, but it is only needed on alternate cycles, so it
can be just an extra 1RW block, per memory. This gives 3 x 1RW per memory, or 6
x 1RW total.

Nice thing is, this extra 2 x 1RW per write port is amortized as you add read
ports:
   1W1R = 6 x 1RW (instead of 4)
   1W2R = 10 x 1RW (instead of 8)
   etc.

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