[Libre-soc-bugs] [Bug 812] invalid access to 0x0 on startup leads to core hang

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=812

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
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                 CC|                            |lkcl at lkcl.net

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to tpearson from comment #0)

> With the current ls2/soc/nmigen versions, the CPU core reset appears to be
> overridden by the default nmigen soc reset, and both resets appear to be
> released at the same time.

sorry, something undocumented and i forgot to tell you

use "make microwatt_external_core_bram" back in soc to get it to create
a version of external_core_top.v that has its reset at 0xff00_0000
or "make microwatt_external_core_spi" if you want one that has its reset
at 0xf000_0000

> I am working on staggering the main rst pulse and the CPU reset pulse to fix
> this problem.

the above make targets should in theory ensure that doesn't happen.

look in external_core_top.v for this:

          \dec2_cur_pc$next  = 64'h00000000ff000000;
          \dec2_cur_msr$next  = 64'h8000000000000001;

and other occurrences of h0000000f0000000

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