[Libre-soc-bugs] [Bug 805] gram randomly comes up in an unworkable condition

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=805

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
part of the solution here is to take the rather drastic but necessary
step of altering the nmigen API by adding a reset line to the Pin
data structure.

there's really no other way to get down to the DDR Instances with
the reset signal needed.

whilst investigating i noticed that the assumption that the reset pads
are "straight" (xdr=1) is wrong: they're also supposed to be 4x phased
(xdr=4), which is quite fascinating, it means that rising and falling
edge *reset* lines do different things inside the DRAM IC.

i've now wired up all the DRAM pad resets to ResetSignal("dramsync")
which in theory should start to get stability.  an early check showed
that yes they were locking much more often.  making rst xdr=4 should
also help, it meant that 1/2 the IOpads were not being properly reset
at all (hm)

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