[Libre-soc-bugs] [Bug 806] New: Nest should be able to run at different clock rate than main CPU

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=806

            Bug ID: 806
           Summary: Nest should be able to run at different clock rate
                    than main CPU
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Other
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: tpearson at raptorengineering.com
                CC: libre-soc-bugs at lists.libre-soc.org
   NLnet milestone: ---

The main CPU maximum frequency currently limits the overall speed of the SoC,
including the "nest" (DRAM controller, HyperRAM, etc.) due to the use of a
synchronous clock Wishbone interconnect.

The CPU and any synchronous peripherals (e.g. UART, other low-speed
"southbridge" components) should be moved to their own clock domain on a
dedicated Wishbone bus, then bridged in with an asynchronous converter to the
high speed nest bus.

In ASIC a similar design will be needed, but in that case the CPU will be
running faster than the nest, and a third even slower bus would be used for the
southbridge.

Implementation is in progress, this bug report is a placeholder and a location
to track progress.

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