[Libre-soc-bugs] [Bug 806] Nest should be able to run at different clock rate than main CPU

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=806

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |lkcl at lkcl.net

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
@@ -276,6 +278,8 @@ class DDR3SoC(SoC, Elaboratable):
         #       |     |
         #       +--+--+
         #          |
+        #      WBAsyncBridge
+        #          |
         #      64to32DownCvt
         #          |


ah, i was expecting / thinking that should
go explicitly on the DRAM controller.

speed of other peripherals does not matter (at all)
and having more running at 100 mhz (64to32, uart,
arbiter) actually risks more combinatorial gate
delay and not making 100mhz.

ultimately the async bridge is a temporary hack that
has to go, pending Async FIFOs going in the actual
DRAM controller at the DFII level, or even connecting
directly to the PHY

also doing things that way is much less disruptive
a patch.

-- 
You are receiving this mail because:
You are on the CC list for the bug.