[Libre-soc-bugs] [Bug 784] Implement cl* instructions for carry-less operations

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=784

--- Comment #10 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #6)
> my intuition tells me that this may prove useful, to replace the use
> of an adder.
> 
> https://git.libre-soc.org/?p=nmutil.git;a=blob;f=src/nmutil/ripple.py;hb=HEAD

actually that ripple logic is exactly what I was trying to avoid...it would
generate a 64-deep chain of gates. binary addition is optimized by yosys to use
carry look-ahead (they can be depended on not to break that since it would make
all binary arithmetic have such a huge latency that basically all cpus using
yosys would no longer meet timing).

> 
> relying on yosys to spot that certain gates are redundant is not sensible.

it's perfectly sensible since the xor gates have unused outputs therefore they
are trivially removed by `opt` (after the addition is converted to individual
gates). `abc` (run by synth -- abc is a totally different project that couldn't
realistically be borked by yosys's developers too) also has passes to remove
unused gates.

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