[Libre-soc-bugs] [Bug 737] in-order single-issue Power ISA 3.0 core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=737

--- Comment #29 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cesar Strauss from comment #28)

> Sure.
> 
> I can start fixing TestIssuerInternal FSMs to be forward-chain only, if it
> helps. 

i think it will: then, when copying them to make the pipelines, actually
that becomes trivial.

> In that case, I would leave the Fetch/Decode pipelines for later.

i think it is an important intermediary step, that makes the creation
of pipelines almost trivial, especially when you can see how i split
out FetchFSM: actually the changes needed to make that "true" pipeline
are negligeable.

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