[Libre-soc-bugs] [Bug 737] in-order single-issue Power ISA 3.0 core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=737

--- Comment #28 from Cesar Strauss <cestrauss at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #27)
> yehyeh. this makes it... awkward to turn into separate FSMs, which then
> in turn can be morphed into pipelines
> perhaps by cutting out SVP64 entirely first it would become much easier
> everything should be a forward-chain (only)

Sure.

I can start fixing TestIssuerInternal FSMs to be forward-chain only, if it
helps. In that case, I would leave the Fetch/Decode pipelines for later.

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