[Libre-soc-bugs] [Bug 737] in-order single-issue Power ISA 3.0 core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=737

--- Comment #27 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
IRC log notes

lkcl    yehyeh. this makes it... awkward to turn into separate FSMs, which then
in turn can be morphed into pipelines   19:49
lkcl    perhaps by cutting out SVP64 entirely first it would become much easier
19:50
lkcl    everything should be a forward-chain (only)     19:53
lkcl    with the sole exception being:  19:53
lkcl    * reading of PC (if it is detected to have been changed by TRAP or
BRANCH)      19:54
lkcl    * reading of MSR (same, by TRAP or MTMSR)       19:54
lkcl    * a global stall condition      19:54
lkcl    * a global "core reset" condition       19:55
lkcl    that's pretty much it: that's the only "backwards" feedback, from later
stages to earlier ones, and even PC and MSR are via the regfile (already), not
by special datapaths     19:56
lkcl    oh, of course, the exception flags, from LDST.  19:58
lkcl    those are also backwards-propagated     19:58
lkcl    under... guess what: stall conditions of course :)

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