[Libre-soc-bugs] [Bug 737] in-order single-issue Power ISA 3.0 core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=737

--- Comment #26 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cesar Strauss from comment #25)
> Current plan for the in-order pipelined issuer:
> 
> * Create pipelined_issuer.py in src/soc/simple (alongside issuer.py).

to help with clarity on that, what i think i will do this afternoon is split
out fetch_fsm into its own submodule.  it is one of the few with clear
in/out ready/valid signalling, whereas some of the others have dual
ready/valid.  planning ahead back when TestIssuerInternal was being developed,
they shouldn't have had, but hey.

> * Copy interface and initialization code from TestIssuerInternal into
> PipelinedIssuer class, so that one can be substituted for the other
> transparently.

good idea

> * Add an argument to test_issuer.py, to instantiate a PipelinedIssuer module
> instead of TestIssuerInternal. Likely, need to adjust HDLRunner in
> https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/test/
> test_runner.py;h=03d4fe96197706bd8c52b9fc28d3cd8952dc05cf;hb=HEAD#l132

yes, that one bypasses TestIssuer itself due to the clock-domain
crossing and the (optional) addition of a PLL and other things,
none of which are relevant for actual instruction running in
a unit test environment.

-- 
You are receiving this mail because:
You are on the CC list for the bug.