[Libre-soc-bugs] [Bug 737] in-order single-issue Power ISA 3.0 core

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon Nov 22 10:14:38 GMT 2021


--- Comment #25 from Cesar Strauss <cestrauss at gmail.com> ---
Current plan for the in-order pipelined issuer:

* Create pipelined_issuer.py in src/soc/simple (alongside issuer.py).

* Copy interface and initialization code from TestIssuerInternal into
PipelinedIssuer class, so that one can be substituted for the other

* Add an argument to test_issuer.py, to instantiate a PipelinedIssuer module
instead of TestIssuerInternal. Likely, need to adjust HDLRunner in

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