[Libre-soc-bugs] [Bug 737] in-order single-issue Power ISA 3.0 core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=737

--- Comment #25 from Cesar Strauss <cestrauss at gmail.com> ---
Current plan for the in-order pipelined issuer:

* Create pipelined_issuer.py in src/soc/simple (alongside issuer.py).

* Copy interface and initialization code from TestIssuerInternal into
PipelinedIssuer class, so that one can be substituted for the other
transparently.

* Add an argument to test_issuer.py, to instantiate a PipelinedIssuer module
instead of TestIssuerInternal. Likely, need to adjust HDLRunner in
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/test/test_runner.py;h=03d4fe96197706bd8c52b9fc28d3cd8952dc05cf;hb=HEAD#l132

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